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tda7309 digital controlled stereo audio processor with loudness input multiplexer: 3 stereo inputs record output function loudness function volume control in 1db steps independent left and right volume control soft mute function all functions programmable via se- rial i 2 c bus description the tda7309 is a control processor with inde- pendent left and right volume control for quality audio applications. selectable external loudness and soft mute functions are provided. control is accomplished by serial i 2 c bus micro- processor interface. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and low dc stepping are obtained. september 2003 ? 17 18 13 14 11 input selector left inputs right inputs supply 16 7 15 volume + loudness soft mute 19 loud(l) 22 m f cref 12 loud(r) mute mute 6 4 5 8 9 2 out left scl sda diggnd out right addr d93au045a bus serial bus decoder + latches 20 3 x 2.2 m f 3 x 2.2 m f volume + loudness agnd v s 3 csm 100nf 100nf tda7309 10 recout(r) 1 recout(l) block diagram dip20 so20 ordering number: tda7309 tda7309d 1/12
absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.5 v t amb operating ambient temperature C40 to 85 c t stg storage temperature range C55 to +150 c quick reference data symbol parameter test condition min. typ. max. unit v s operating supply voltage 6 10 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms, f = 1khz 0.01 0.1 % s/n signal to noise ratio 106 db sc channel separation f = 1khz 100 db volume control 1.0db step C95 0 db soft mute attenuation 60 db direct mute attenuation 100 db recoutl outl csm sda scl gnd dgnd add outr 1 3 2 4 5 6 7 8 9 loudr in2r in1r v s cref in1l in2l loudl in3l 20 19 18 17 16 14 15 13 12 d94au058a recoutr 10 in3r 11 pin connection (top view) in1l in2l in3l recoutl in1r in2r in3r recoutr 17 18 20 1 14 13 10 11 19 12 5 4 6 8 ll lr scl sda diggnd add csm 3 2 16 15 cref agnd 7 outl v s outr 9 d94au057a tda7309 test circuit tda7309 2/12
electrical characteristics (refer to the test circuit, t amb = 25 c, v s = 9v, r l = 10k w , r g = 50 w , all controls flat (g = 0), f = 1khz unless otherwise specified.) symbol parameter test condition min. typ. max. unit supply v s supply voltage 5 (*) 9 10 v i s supply current 7 10 ma svr ripple rejection 60 85 db input selectors r i input resistance 35 50 65 k w s in input separation 80 90 db volume control c range control range 92 db a vmax max. attenuation 87 92 95 db a step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -24db -1.2 1.2 db a v = -24 to -56db -3 2 db e t tracking error 2db v dc dc steps adjacent attenuation steps 0 3 mv from 0db to a v max. 0.5 5 mv a mute output mute attenuation 80 100 db soft mute t d delay time c smute = 22nf 0 to C20db fast mode slow mode 1 20 ms ms audio outputs v clip clipping level d = 0.3% 2 2.6 vrms r l output load resistance 2 k w r out output impedance 100 200 300 w v dc dc voltage level 3.8 v general e no output noise bw = 20-20khz, flat output muted all gains = 0db 2.5 515 m v m v a curve all gains = 0db 3 m v et total tracking error a v = 0 to C24db a v = -24 to C56db 0 0 1 2 db db s/n signal to noise ratio all gains = 0db; v o = 1vrms 95 106 db d distortion 0.01 0.1 % s c channel separation 80 100 db bus inputs v il input low voltage 1 v v ih input high voltage 3 v i in input current v in = 0.4v -5 +5 m a v o output voltage sda acknowledge i o = 1.6ma 0.4 0.8 v (*) hedevice work until 5v but no guarantee about svr thermal data symbol parameter so20 dip20 unit r th j-pins thermal resistance junction to pins 150 100 c/w tda7309 3/12
figure 1: noise vs. volume setting. figure 3: thd vs. frequency figure 5: channel separation vs. frequency. figure 4: thd vs. r load . figure 6: output clip level vs. supply voltage. figure 2: svrr vs. frequency. tda7309 4/12
figure 7: quiescent current vs. supply voltage. figure 9: loudnes vs. frequency (c loud = 100nf) vs. volume figure 10: loudness vs. external capacitors figure 8: loudness vs. volume attenuation. tda7309 5/12
i 2 c bus interface data transmission from microprocessor to the tda7313 and viceversa takes place thru the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). data validity as shown in fig. 11, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig. 12 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tran- sition of the sda line while scl is high. byte format every byte transferred on the sda line must con- tain 8 bits. each byte must be followed by an ac- knowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 13). the peripheral (audioprocessor) that ac- knowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can gen- erate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio- processor, the m p can use a simplier transmis- sion: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity. figure 11: data validity on the i 2 cbus figure 12: timing diagram of i 2 cbus figure 13: acknowledge on the i 2 cbus tda7309 6/12
sda, scl i 2 cbus timing symbol parameter min. typ. max. unit f scl scl clock frequency 0 400 khz t buf bus free time between a stop and start condition 1.3 m s t hd:sta hold time (repeated) start condition. after this period, the first clock pulse is generated 0.6 m s t low low period of the scl clock 1.3 m s t high high period of the scl clock 0.6 m s t su:sta set-up time for a repeated start condition 0.6 m s t hd:da data hold time 0.300 m s t su:dat data set-up time 100 ns t r rise time of both sda and scl signals 20 300 ns (*) t f fall time of both sda and scl signals 20 300 ns (*) t su:sto set-up time for stop condition 0.6 m s all values referred to v ih min. and v il max. levels (*) must be guaranteed by the i 2 c bus master. sda scl t buf p s t hd;sta t low t r t f t hd;dat t su;dat t high t f sr p t su;sta t hd;sta t sp t su;sto d95au314 p = stop s = start definition of timing on the i 2 c-bus tda7309 7/12
software specification interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the tda7309 address (the 8th bit of the byte must be 0). the tda7309 must always acknowledge at the end of each transmitted byte. a sequence of data (n-bytes + acknowledge) a stop condition (p) tda7309 address msb first byte lsb msb lsb msb lsb s001100a0 ack data ack data ack p data transferred (n-bytes + acknowledge) ack = acknowledge s = start p = stop max clock speed 100kbits/s software specification chip address msb lsb 00110010 pin address open 00110000 pin address close to ground msb f6 f5 f4 f3 f2 f1 lsb volume 0xxxxxxx mute/loud 1 00xxxxx inputs 1 01xxxxx channel 1 10xxxxx channel abilitation codes msb f6 f5 f4 f3 f2 f1 lsb function 1 1 0 channel x x x 0 0 right x x x 0 1 left x x x 1 0 both x x x 1 1 both power on reset condition 1 1 1 1 1 1 1 0 function codes tda7309 8/12
msb f6 f5 f4 f3 f2 f1 lsb function 0 step 1db 000 0db 0 0 1 -1db 0 1 0 -2db 0 1 1 -3db 1 0 0 -4db 1 0 1 -5db 1 1 0 -6db 1 1 1 -7db 0 step 8db 0000 0db 0001 -8db 0010 -16db 0011 -24db 0100 -32db 0101 -40db 0110 -48db 0111 -56db 1000 -64db 1001 -72db 1010 -80db 1011 -88db 1 1 x x mute mute loudness codes msb f6 f5 f4 f3 f2 f1 lsb function 1 0 0 mute/loud x 0 0 slow soft mute on x 0 1 fast soft mute on 1 soft mute off 1 loud off x 0 0 loud on (10db) x 1 0 loud on (20db) input multiplexer codes msb f6 f5 f4 f3 f2 f1 lsb function 101 inputs xxx0 0 mute x x x 0 1 in2 x x x 1 0 in3 x x x 1 1 in1 volume codes purchase of i 2 c components of sgs-thomson microlectronics, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. tda7309 9/12
dip20 dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 outline and mechanical data tda7309 10/12
11 0 11 20 a e b d e l k h a1 c so20mec h x 45? so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k 0? (min.)8? (max.) outline and mechanical data tda7309 11/12
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia C belgium - brazil - canada - china C czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com tda7309 12/12

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